1. Field of the Invention
The present invention relates to an encoder apparatus and a decoder apparatus suitably used to transmit digital data that represent six types of state transitions through three transmission lines.
2. Description of the Related Art
Generally, when data are transmitted between a computer device and peripheral devices, data are transmitted between multiprocessors, a digital video signal is transmitted, digital data are converted into serial data to decrease the number of transmission lines. This system has been widely used as the serial transmission. When the serial transmission system is used, the reception side uses a clock that represents transmission timing of information bits represented by “0's” and “1's” so that the reception side correctly reproduces the information bits transmitted through a transmission line.
When data and a clock are transmitted by the serial transmission, they may be separately transmitted. Instead, they may be chronologically multiplexed and transmitted. When data and a clock are separately transmitted, at least four transmission lines are used. In contrast, when data and a clock are chronologically multiplexed and transmitted, only two or three transmission lines are used. Thus, the latter method is advantageous over the former method of which data and a clock are separately transmitted.
The system of which data and a clock are chronologically multiplexed and transmitted through two transmission lines (hereinafter this system is referred to as the two-line system) has been practically used for example as a system that encodes a clock together with data according to an encoding system called Manchester encoding and that transmits a multiplexed signal through a common transmission line. In the two-line system of the related art, the clock is reproduced using Phase Locked Loop (PLL). Thus, hardware of the demodulating section becomes complicated. In addition, if a more faster communication speed is desired, the PLL cannot follow the clock frequency, thereby preventing the clock from being reproduced.
In a system that uses three transmission lines (hereinafter this system is referred to as the three-line system), data and a clock are represented by three-bit signals made up of one or two “0's” and one or two “1's”. In the three-line system, data and a clock are detected by state transitions of three signals transmitted through the three transmission lines. Since the demodulation side does use the PLL, the three-line system allows data to be communicated at higher rate than the two-line system.
On the other hand, since signals in the transmission lines of the three-line system are not balanced, there is a higher possibility of which a problem such as Electro Magnetic Interference (EMI) takes place at a signal change point. When signals of three bits transmitted through three transmission lines change from “100” to “011”, a problem such as the EMI tends to take place. To solve this problem, signals are encoded so that the total of voltages of the signals transmitted through the three transmission lines becomes constant before and after the signals change. This cannot be accomplished with two signal states “0” and “1”. Thus, three types of voltages are provided. Hereinafter, these signals are referred to as the three-value three-differential logic signals.
Patent Document 1 describes a data transmission method and a transmission device that transmit data with three-value three-differential logic signals. In Patent Document 1, on the transmission side, a modulator samples input serial digital data, converts them into three binary logic signals, converts them into three-value three-differential logic signals, and outputs them to three transmission lines. Conversely, the reception side converts the three-value three-differential logic signals transmitted through the three transmission lines into three binary logic signals. A demodulator restores the three binary logic signals to the original serial data.    [Patent Document 1] Japanese Patent No. 3360861
FIG. 1 shows an example of the structure of the modulator of Patent Document 1. FIG. 2 and FIG. 3 show state transition tables of a modulation logic circuit 102 used in the modulator. The modulator is made up of three D type flip-flops 101u, 101v, and 101w and a modulation logic circuit 102. The three D type flip-flops 101u, 101v, and 101w each have a clock input terminal to which a clock Ci is input. The modulation logic circuit 102 receives serial digital data Di and latch output data DFu, DFv, and DFw of the D type flip-flops 101u, 101v, and 101w. The modulator has six types of output states from state number 1 to state number 6. When the input serial digital data Di are logic “H”, as shown in FIG. 2, whenever the clock Ci goes high, the state number is decremented by 1. When the serial digital data Di is logic “L”, as shown in FIG. 3, whenever the clock Ci goes high, the state number is incremented by 1. The modulation logic circuit 102 outputs three binary logic signals corresponding to the state numbers.
FIG. 4 shows an example of the structure of the demodulator of Patent Document 1. The demodulator performs a demodulation operation shown in FIG. 5 corresponding to the modulation operation of the modulator 100 and restores the original serial digital data. In the demodulator, a clock reproduction circuit 31 is made up of a clock demodulation logic circuit 32, a differentiation circuit 33, and an absolute value circuit 34. The clock demodulation logic circuit 32 detects whether the logics of the input transmission data Iu, Iv, and Iw are “H” or “L” and outputs logic values corresponding to the current state numbers shown in FIG. 6. The differentiation circuit 33 differentiates outputs of the clock demodulation logic circuit 32 and obtains a change of the clock. The absolute value circuit 34 obtains an leading edge pulse of the differentiation output of the differentiation circuit 33 as a reproduction clock Co.
The clock reproduction circuit 31 supplies the reproduction clock Co reproduced from the input data Iu, Iv, and Iw to clock input terminals of the flip-flops 35u, 35v, 35w, 36u, 36v, and 36w and outputs the reproduction clock Co to the outside of the demodulator. The flip-flops 35u, 35v, and 35w perform latch operations in synchronization with the reproduction clock Co so as to hold the current transmission data Iu, Iv, and Iw for one clock period. Latch output data QMu, QMv, and QMw of the flip-flops 35u, 35v, and 35w are input to data input terminals of the flip-flops 36u, 36v, and 36w and supplied to a demodulation logic circuit 37.
The flip-flops 36u, 36v, and 36w perform latch operations in synchronization with the reproduction clock Co. The flip-flops 36u, 36v, and 36w holds the latch output data QMu, QMv, and QMw of the flip-flops 35u, 35v, and 35w for one more clock period. Latch output data QLu, QLv, and QLw of the flip-flops 36u, 36v, and 36w are supplied to the demodulation logic circuit 37.
The demodulation logic circuit 37 compares the latch output data QMu, QMv, and QMw of the flip-flop 35u, 35v, and 35w, namely current input transmission data, with the latch output data QLu, QLv, and QLw of the flip-flops 36u, 36v, and 36w, namely one-clock-period prior input transmission data to reproduce serial digital data and output them as output data.